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Integrated Circuit Systems, Inc.
ICS950402
AMD - K8TM System Clock Chip
Recommended Application: AMD K8 System Clock with AMD or VIA Chipset Output Features: * 2 - Differential pair push-pull CPU clocks @ 3.3V * 9 - PCICLK (Including 1 free running) @3.3V * 4 - Selectable PCICLK/HTTCLK @3.3V * 1 - 48MHz, @3.3V fixed. * 1 - 24/48MHz @ 3.3V * 3 - REF @3.3V, 14.318MHz. Features: * Programmable output frequency. * Programmable output divider ratios. * Programmable output rise/fall time. * Programmable output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/ write operations. * Uses external 14.318MHz crystal. * Supports Hyper Transport Technology (HTTCLK).
Pin Configuration
*FS0/REF0 VDDREF X1 X2 GND *(PCICLK7/HTTCLK0)ModeA *PCICLK8/HTTCLK1/ModeB PCICLK9/HTTCLK2 VDDPCI GND PCICLK10/HTTCLK3 PCICLK11 PCICLK0 PCICLK1 GND VDDPCI ****PCICLK2 ****PCICLK3 VDDPCI GND PCICLK4 PCICLK5 ~*PCICLK_F/ModeC ~*(PCICLK6)PCI_STOP# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS1* GND VDDREF REF2/FS2* Reset# VDDA GND CPUCLK8T0 CPUCLK8C0 GND VDDCPU CPUCLK8T1 CPUCLK8C1 VDDCPU GND GND VDD 48MHz/FS3** GND AVDD48 24_48MHz/Sel24_48#*~ GND SDATA SCLK
48-Pin TSSOP/SSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength **** This Output has 2.3X Drive Strength
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50
REF (2:0)
CPU DIVDER
Stop
CPUCLKC (1:0) CPUCLKT (1:0)
SDATA SCLK FS (3:0) MODE (A,B,C) PCI_STOP# 24_48SEL#
Control Logic Config. Reg.
PCI DIVDER
Stop
PCICLK (6:0, 11) PCICLK_F
X2
PCICLK/HTTCLK (3:0)
0700B--04/30/04
ICS950402
ICS950402
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME *FS0/REF0 VDDREF X1 X2 GND *(PCICLK7/HTTCLK0)ModeA *PCICLK8/HTTCLK1/ModeB PCICLK9/HTTCLK2 VDDPCI GND ~PCICLK10/HTTCLK3 PCICLK11 PCICLK0 PCICLK1 GND VDDPCI ****PCICLK2 ****PCICLK3 VDDPCI GND PCICLK4 PCICLK5 ~*PCICLK_F/ModeC ~*(PCICLK6)PCI_STOP# SCLK SDATA GND 24_48MHz/Sel24_48#*~ AVDD48 GND 48MHz/FS3** VDD GND GND VDDCPU CPUCLK8C1 CPUCLK8T1 VDDCPU GND CPUCLK8C0 CPUCLK8T0 GND VDDA Reset# REF2/FS2* VDDREF GND REF1/FS1* PIN TYPE I/O PWR IN OUT PWR I/O I/O OUT PWR PWR OUT OUT OUT OUT PWR PWR OUT I/O PWR PWR OUT OUT I/O I/O IN I/O PWR I/O PWR PWR I/O PWR PWR PWR PWR OUT OUT PWR PWR OUT OUT PWR PWR OUT I/O PWR PWR I/O DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. PCI clock output / Hyper Transport output / Mode selection pin, this input is activated by the ModeB selection pin. PCI clock output / Hyper Transport output / Mode selection latch input pin. PCI clock output / Hyper Transport output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output / Hyper Transport output. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Real time system reset signal for watchdog timer timeout. This signal is active low and selected by Mode latch input / 3.3V PCI clock clock output. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low / PCI clock output, this output is activated by the Mode selection pin Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. Free running PCI clock not affected by PCI_STOP# / Mode selection latch input pin. PCI clock output, this output is activated by the Mode selection pin / Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant Ground pin. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V Ground pin. Frequency select latch input pin / Fixed 48MHz clock output. 3.3V Power supply, nominal 3.3V Ground pin. Ground pin. Supply for CPU clocks, 3.3V nominal "Complimentary" clocks of differential 3.3V push-pull K8 pair. "True" clocks of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Ground pin. "Complimentary" clocks of differential 3.3V push-pull K8 pair. "True" clocks of differential 3.3V push-pull K8 pair. Ground pin. 3.3V power for the PLL core. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. 14.318 MHz reference clock / Frequency select latch input pin. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 2X Drive Strength **** This Output has 2.3X Drive Strength
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ICS950402
General Description
The ICS950402 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer systems. The ICS950402 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Power Groups
Pin Number AVDD 2 29 32 43 VDD 9 16, 19 35, 38 46 GND 5 27, 30 33 42 GND 10 15, 20 34, 39 47 PCI33_HT66outputs PCI33 outputs CPU outputs REF Description Crystal 48MHz fixed, Fix Analog, Fix Digital CPU Master Clock, CPU Analog
Mode Functionality Tables
ModeA 0 0 1 1 ModeB 0 1 0 1 Pin6 HTTCLK0 ModeA (Input Only) PCICLK7 ModeA (Input Only) Pin7 HTTCLK1 HTTCLK1 PCICLK8 PCICLK8 Pin8 HTTCLK2 HTTCLK2 PCICLK9 PCICLK9 Pin11 PCICLK10 HTTCLK3 PCICLK10 PCICLK10
ModeC 0 1
Pin24 PCICLK6 PCI_STOP#
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ICS950402
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
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Not acknowledge stoP bit
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ICS950402
Table1: Frequency Selection Table
Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit3 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit2 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 100.00 133.33 166.66 200.00 103.00 137.33 171.66 206.00 154.50 185.40 216.30 247.20 278.10 240.33 274.67 309.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 66.67 66.67 66.66 66.67 68.67 68.66 68.66 68.67 61.80 61.80 72.10 61.80 69.53 68.67 68.67 77.25 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 33.33 33.33 33.33 33.33 34.33 34.33 34.33 34.33 30.90 30.90 36.05 30.90 34.76 34.33 34.33 38.63 VCO MHz 403.60 535.60 672.00 404.00 400.80 534.00 666.80 400.80 600.00 360.00 420.00 480.00 540.00 466.66 533.34 600.00 400.00 533.32 666.64 400.00 412.00 549.32 686.64 412.00 618.00 370.80 432.60 494.40 556.20 480.66 549.34 618.00
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ICS950402
I2C Table: Functionality and Frequency Control Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Control Function Write Disable S/W Control SPREAD Enable FS4 FS3 FS2 FS1 FS0 Write Enable S/W Control Type RW RW RW RW RW RW RW RW 0 Disable Disable 1 Enable Enable PWD 0 0 0 0 0 0 0 0
See Table1: Frequency Selection Table
Disable
Enable
I2C Table: Output Control Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 6 22 21 18 17 14 13 Pin # Name PCICLK8/HTTCLK1 PCICLK7/HTTCLK0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
I2C Table: Output Control Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 37/36 41/40 45 48 1 28 31 8 Pin # Name CPUT/C_1 CPUT/C_0 REF2 REF1 REF0 24_48MHz 48MHz PCICLK9/HTTCLK2 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
I2C Table: PCI Free-Run Control Register
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 12 11 22 21 18 17 14 13 Pin # Name PCICLK11 PCICLK10 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control PCI_STOP# Control Type RW RW RW RW RW RW RW RW 0 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable 1 Free Run Free Run Free run Free run Free run Free run Free run Free run PWD 0 0 0 0 0 0 0 0
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ICS950402
I2C Table: Read back and Output Control Register
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 23 12 11 Pin # Name PCICLK_F PCICLK11 24_48SEL FS3 FS2 FS1 FS0 PCICLK10/HTTCLK3 Control Function Output Control Output Control Output Control Type RW RW R R R R R RW 0 Disable Disable Disable 1 Enable Enable Enable PWD 1 1 1 1 1 1 1 1
I2C Table: Vendor and Revision ID Register
Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 1
I2C Table: Byte Count Register
Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 1 1 1
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
I2C Table: Output Control Register
Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0 Control Function REVISION ID Type R R R R R R R R 0 1 PWD 0 0 0 0 0 0 0 1
VENDOR ID
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ICS950402
I2C Table: Output Control Register
Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
I2C Table: Watchdog Timer Register
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Control Function These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 290ms =4.64 seconds Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 1 0 0 0 0
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 7 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name M/NEN WDEN WDRB WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 Control Function M/N Programming Enable Watchdog Enable WD Alarm Status Bit Writing to these bit will configure the safe frequency as Byte0 bit (5:1) Type RW RW R RW RW RW RW RW 0 Disable Disable Normal 1 Enable Enable Alarm PWD 0 0 X 0 0 0 0 1
I2C Table: VCO Frequency Control Register
Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div (6:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
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ICS950402
I2C Table: VCO Frequency Control Register
Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function The decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Reserved Reserved It is recommended to use ICS Spread % table for spread programming. Type R R R RW RW RW RW RW 0 1 PWD 0 0 1 X X X X X
I2C Table: Output Divider Control Register
Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCI / HTTDiv3 PCI / HTTDiv2 PCI / HTTDiv1 PCI / HTTDiv0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function PCI(9:7)/HTT(2:0) divider ratio can be configured via these 4 bits individually. CPU divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
See Table 2: Divider Ratio Combination Table
See Table 2: Divider Ratio Combination Table
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ICS950402
I2C Table: Output Divider Control Register
Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved PCIDiv3 PCIDiv2 PCIDiv1 PCIDiv0 Control Function Reserved Reserved Reserved Reserved PCI divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
See Table 2: Divider Ratio Combination Table
Table 2: CPU, HTT & PCI Divider Ratio Combination Table
Divider (3:2) Bit 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 8 12 20 28 Div 01 0100 0101 0110 0111 Address 4 6 10 14 Div 10 1000 1001 1010 1011 Address 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 4 6 10 14 Div Divider (1:0)
I2C Table: Output Divider Control Register
Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved HTTINV CPUINV PCI DIV3 PCI DIV2 PCI DIV1 PCI DIV0 Control Function Reserved Reserved HTT Phase Invert CPU Phase Invert PCI10/HTTCLK3 divider ratio can be configured via these 4 bits Type RW RW RW RW RW RW RW RW 0 Default Default 1 Inverse Inverse PWD X X X X X X X X
See Table 2: Divider Ratio Combination Table
I2C Table: Group Skew Control Register
Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
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ICS950402
I2C Table: Group Skew Control Register
Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 PCI/HTTSkw3 PCI/HTTSkw2 PCI/HTTSkw1 PCI/HTTSkw0 Control Function CPU-PCI(6:0) Skew Control Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
See Table 3: 7-Steps Skew Programming Table
CPU-PCI(10:7) / HTT(2:0) Skew Control
See Table 3: 7-Steps Skew Programming Table
Table 3: 7-Steps Skew Programming Table
7 Step 11 10 01 00 MSB 11 900 ps N/A N/A N/A 10 750 ps N/A N/A N/A 01 600 ps N/A N/A N/A 00 450 ps 300 ps 150 ps 0.0 ps LSB
I2C Table: Group Skew Control Register
Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 1 1 1 1
I2C Table: Slew Rate Control Register
Byte 21 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved GSR_EN ASEL AEN Control Function Reserved Reserved Reserved Reserved Reserved Gearshift Reset Enable Async Frequency Select Async Frequency Enable Type RW RW RW RW RW RW RW See Table 4 for Async Freq RW 1 0 Disable 1 Enable PWD 0 0 0 0 0 0 0
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ICS950402
Table 4: Asynchronous Fix PLL Frequency Select Table controlled by Byte 21 bits (1:0)
Byte 21 Bit 1 0 0 1 1 Byte 21 Bit 0 0 1 0 1 VCO FREQ 528 Main PLL 528 Main PLL HTT DIV 8 X 7 X HTT FREQ 66 Main PLL 74.4286 Main PLL PCI DIV 8 X 7 X PCI FREQ 33 Main PLL 37.7143 Main PLL 48 DIV 11 X 11 X 48 FREQ 48 48 48 48 REF FREQ 14.318 14.318 14.318 14.318
I2C Table: Drive Strength Control Register
Byte 22 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCI10/HTT3 DrCntrl PCI6Drv PCI3Drv PCI2Drv PCIFDrv 24_48Drv Reserved Reserved Control Function PCICLK10/HTTCLK3 Drive Strength Control PCICLK6 Drive Strength Control PCICLK3 Drive Strength Control PCICLK2 Drive Strength Control PCICLK_F Drive Strength Control 24_48MHz Drive Strength Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1X 1X 1.2X 1.2X 1X 1X 1 2X 2X 2.3X 2.3X 2X 2X PWD 1 1 1 1 1 1 1 1
I2C Table: Slew Rate Control Register
Byte 23 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved SDRSlw1 SDRSlw0 PCISlw1 PCISlw0 PCISlw1 PCISlw0 Control Function Reserved Reserved PCICLK(9:7)/HTTCLK (2:0) Slew Rate Control PCICLK(3:0) Slew Rate Control PCICLK(11,8, 6:4) Slew Rate Control Type RW RW RW RW RW RW RW RW 0 1 PWD X X 1 0 1 0 1 0
I2C Table: Slew Rate Control Register
Byte 24 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name REFSlw1 REFSlw0 48MSlw1 48MSlw0 48MSlw1 48MSlw0 Reserved Reserved Control Function REF(2:0) Slew Rate Control 48MHz Slew Rate Control 24_48MHz Slew Rate Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 0 1 0 1 0 1 1
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ICS950402
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +3.8 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . Input ESD protection usung human body model > 1KV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH Input Low Current IIL1 Input Low Current VIL2 IDD3.3OP66 Max loads; Select @ 100MHz Operating Supply Current IDD3.3OP133 Max loads; Select @ 133MHz Power Down PD Input frequency Fi VDD = 3.3 V Input Capacitance1 Clk Stabilization1
1
MIN 2 VSS - 0.3 -5 -200
TYP
MAX UNITS VDD + 0.3 V 0.8 V 5 uA uA uA 250 600 16 5 45 3 mA uA MHz pF pF ms
171 183 12 27 14.318
CIN CINX TSTAB
Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% of target frequency
Guaranteed by design, not 100% tested in production.
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ICS950402
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN VO=VX Output Impedance ZO1 1 Output High Voltage VOH2B Output Low Voltage VOL2B IOL2B VOL = 0.3 V Output Low Current 18 1 1 VT = 50% dt2B Duty Cycle 45 Jitter, Cycle-to-cycle VDIFF1,2
1
TYP 50
MAX 1.2 0.4
49 70 1.9
52 200 2.3
UNITS V V mA % ps V
tjcyc-cyc2B
VT = VX
0 0.4
Differential Voltage, measured @ the Hammer test load (single-ended measurement) Change in VDIFF_DC magnitude, measured @ the Hammer test load (single-ended measurement) Common Mode Voltage, measured @ the Hammer test load (single-ended measurement) Change in Common Mode Voltage, measured @ the Hammer test load (single-ended measurement)
VDIFF
1
-150
80
150
mV
VCM
1,2
1.45
1.6
1.85
V
VCM
1
-200
45
200
mV
Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - Test circuit: Rs=15, CL=5pF, Vterm=100 between CPUT, CPUC
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ICS950402
Electrical Characteristics - PCICLK, PCICK33 / HT66 (33MHz)
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate1 SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20 - 60%, 1X drive strength 2X drive strength 2.3X drive strength Measured from 60 - 20%, 1X drive strength 2X drive strength 2.3X drive strength VT = 1.5 V Measured on rising edge @ 1.5V VO = VX MIN 2.4 TYP MAX 0.4 -15 10 0.9 1 1 45 -1000 ZO 0.92 1.38 1.63 1.15 1.93 2.19 51 140 450 265 UNITS V V mA mA V/ns
4
Fall Edge Rate1 Duty Cycle1 Jitter, Cycle-to-Cycle1 Jitter, Accumulated1 Output Impedance
1
tf1 dt1 tcyc-cyc1
4 55 250 1000 500
V/ns % ps ps ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICK33 / HT66 (66MHz)
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Edge Rate1 Fall Edge Rate1 Duty Cycle1 Jitter, Cycle-to-Cycle1 Jitter, Accumulated1 Output Impedance
1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tcyc-cyc1 ZO
CONDITIONS IOH = -12 mA IOL = 9.0 mA VOH = 2.0 V VOL = 0.8 V Measured from 20 - 60%, 1X drive strength 2.3X drive strength Measured from 60 - 20%, 1X drive strength 2.3X drive strength VT = 1.5 V Measured on rising edge @ 1.5V VO = VX
MIN 2.4
TYP
MAX 0.4 -15
10 0.9 1 1 45 -1000
UNITS V V mA mA V/ns V/ns % ps ps ps
0.95 1.65 1.18 2.12 51 200 450 265
4 4 55 250 1000 500
Guaranteed by design, not 100% tested in production.
0700B--04/30/04
15
ICS950402
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA Output Low Voltage VOL5 IOL = 9 mA IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current Rise Edge Rate1 tr5 Measured from 20 - 80% 1 Fall Edge Rate tf5 Measured from 80 - 20% 1 dt5 VT = 50% Duty Cycle Jitter, Cycle-to-Cycle Jitter, Accumulated1
1 1
MIN 2.4
TYP
MAX 0.4 -22
16 0.5 0.5 45 0 -1000
1.3 1.5 54 190 100
2 2 55 1000 1000
UNITS V V mA mA V/ns V/ns % ps ps
tjcyc-cyc5
1
Measured on rising edge @ 1.5V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -12 mA IOL = 9 mA Output Low Voltage VOL5 IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current Measured from 20 - 80%, for 24_48MHz tr5 for 48MHz Rise Edge Rate1 Measured from 80 - 20%, for 24_48MHz tf5 for 48MHz Fall Edge Rate1 1 dt5 VT = 50% Duty Cycle Jitter, Absolute
1 1 1
MIN 2.4
TYP
MAX 0.4 -22
16 0.5 0.5 45 -1 0 0 -1000 20
UNITS V V mA mA V/ns V/ns % ns ps ps ps
2.35 1.30 3.15 1.65 50 0.3 200 260 200
2.5 2 3.5 2 55 1 500 500 1000 60
tjabs5
1 1 1
VT = 1.5 V VT = VX, for 24_48MHz clock VT = VX, for 48MHz clock VO = VX
Jitter, Cycle-to-Cycle Jitter, Accumulated Output Impedance
1 1
tjcyc-cyc5 tjcyc-cyc5 ZO
Jitter, Cycle-to-Cycle
Guaranteed by design, not 100% tested in production.
0700B--04/30/04
16
ICS950402
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248175 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
0700B--04/30/04
17
ICS950402
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 48
10-0039
-Ce
b SEATING PLANE
D mm. MIN 12.40 MAX 12.60 MIN .488
D (inch) MAX .496
aaa C
Reference Doc.: JEDEC Publication 95, MO-153
Ordering Information
ICS950402yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0700B--04/30/04
18
ICS950402
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950402yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0700B--04/30/04
19

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